1. Technical Field
The present invention relates to digital phase locked loop circuits and more particularly to circuits and methods for controlling dither in digitally controlled oscillators.
2. Description of the Related Art
At the heart of digital phase locked loops (DPLLs) is a digitally controlled oscillator (DCO). There is a fundamental difference between a DCO and a conventional VCO (voltage-controlled oscillator), commonly used in analog PLLs. The VCO is controlled by an analog voltage signal and therefore has a continuous tuning range. The DCO is controlled by a digital signal with a finite bit resolution and therefore produces a discrete set of frequencies.
Referring to FIG. 1, a DCO 10 can be modeled as a VCO 12 with a quantizer 14 at a voltage control input. The resulting quantization noise of the DCO 10 degrades DPLL output jitter and phase noise. As shown in FIG. 1, Δf is the minimum DCO frequency spacing. In a linear model, the DCO quantization noise contribution can be estimated using a conventional model of additive uniformly distributed white noise with a variance of (Δf)2/12. The resulting contribution to phase noise (assuming that a loop filter is running at the reference frequency fREF) is given by the following equation (1):
                              L          ⁡                      (                          f              offset                        )                          =                              1            12                    ⁢                                    (                                                Δ                  ⁢                                                                          ⁢                  f                                                  f                  offset                                            )                        2                    ⁢                      1                          f              ref                                                          (        1        )            
Here, foffset is the offset from the carrier frequency. For example, if the DCO runs at f=4 GHz with a minimum frequency step (Δf) of 10 MHz, in a DPLL using a 200 MHz reference clock, the resulting phase noise due to the DCO quantization is −74 dBc/Hz, at a 1 MHz offset. Note that in the time domain, the oscillation period step ΔT due to DCO quantization is given by Δf/f2, or 0.6 ps in the example above.
These numbers are comparable to or above the free-running DCO noise (which arises due to thermal fluctuations). The typical noise performance of a free-running ring oscillator is in the range from −90 dBc/Hz to −80 dBc/Hz to −75 dBc/Hz (at 1 MHz from 4 GHz), resulting in a free-running period jitter range from 0.1 ps to 0.3 ps to 0.7 ps RMS. For comparison, if a coarser DCO is used, with a 40 MHz frequency step, for example, the quantization noise contribution becomes dominant, e.g., −62 dBc/Hz (at 1 MHz from 4 GHz).
A simple way to reduce the impact of the DCO quantization noise is to increase DCO resolution by reducing the minimum frequency step Δf and correspondingly increasing the total number of frequency steps. This approach, however, is often impractical, as it typically results in an unacceptable increase of DCO area and/or power dissipation. Another standard approach to this problem is to dither the DCO between two adjacent frequencies, f and f+Δf, as shown in FIG. 2.
Referring to FIG. 2, a plot showing frequency versus time to demonstrate basic DCO dithering is depicted. The plot shows instantaneous frequency 20 and an effective frequency 22. Dithering effectively results in a much smaller DCO minimum frequency step. An ideal 8-bit dithering modulator promises to reduce Δf by a factor of 28=256. In the example above that would reduce the quantization noise by 48 dB. The effect of quantization noise due to dithering depends on the type of dithering modulator that is used. It is well known that uniform dithering is not very effective in achieving the desired goal of reducing the DCO noise. Eq. 1 can be employed to estimate the effect of uniform dithering as follows:
                              L          ⁡                      (                          f              offset                        )                          =                              1            12                    ⁢                                    (                                                Δ                  ⁢                                                                          ⁢                  f                                                  f                  offset                                            )                        2                    ⁢                      1                          f              DITH                                                          (        2        )            
Here fDITH is the dithering frequency. In conventional DPLLs, fDITH is usually ¼ or ⅛ of the carrier frequency. In the numerical example above, the only effect of uniform dithering with 4 GHz/4=1 GHz is due to spreading the quantization noise over a 5 times wider band than the fREF=200 MHz. The quantization noise is then reduced by just 7 dB, regardless of the number of bits in the modulator.
Noise-shaped dithering is more attractive than uniform dithering, as it reduces in-band noise by pushing the quantization errors into higher frequencies, where they will be naturally attenuated by the DPLL transfer function. The noise contribution of the 1st order Delta-Sigma dithering modulator is given by the following equation:
                              ℒ          ⁡                      (                          f              OFFSET                        )                          =                              1            12                    ⁢                                    (                                                Δ                  ⁢                                                                          ⁢                  f                                                  f                  OFFSET                                            )                        2                    ⁢                      1                          f              DITH                                ⁢                                                    (                                  2                  ⁢                                                                          ⁢                                      sin                    ⁡                                          (                                                                        π                          ⁢                                                                                                          ⁢                          Δ                          ⁢                                                                                                          ⁢                          f                                                                          f                          DITH                                                                    )                                                                      )                            2                        .                                              (        3        )            
At a 1 MHz offset, using the numbers from our numerical example, we get a 44 dB reduction of phase noise, for 1 GHz dithering. It should be noted that Eq. 1 still applies to Delta-Sigma dithering due to the finite number n of bits in the modulator, with Δf replaced by Δf/2n.
The fundamental characteristic of all these approaches to DCO dithering is that they treat the DCO as a standard quantizer and directly apply dithering techniques well-known in the digital to analog conversion/analog to digital conversion (DAC/ADC) literature. As a result, they all produce a finite amount of quantization noise. It should be noted that phase noise contributions given by Eqs. 1-3 all lead to a corresponding increase in DCO jitter.
Wireline communication applications typically require a low phase noise, wide timing range phase locked loop (PLL). While these requirements can be met using traditional charge pump PLL architectures, a high performance digital PLL (DPLL) based solution offers potential advantages in area, testability, and flexibility. Nearly all high-performance DPLL architectures reported in the literature to date incorporate a time to digital converter (TDC) that acts as the loop's phase and frequency detector (PFD). Subject to its quantization limits, a high-resolution TDC generates output signals proportional to the phase error at its input, effectively linearizing the PFD response. It should be noted, however, that reported high performance TDC-based DPLLs have generally been fractional-N, not integer-N synthesizers.
In a fractional-N loop, the phase difference between a feedback clock and a reference clock at the PFD input varies significantly, frequently jumping by as much as a full output clock period from one phase comparison to the next. At 10 GHz output, this results in a 100 ps phase shift, thus making a TDC with resolution on the order of 10- to 20 ps adequate to generate multiple quantization levels. In an integer-N case, by contrast, a PLL with 500 fs rms jitter at the output and a typical feedback divider value in the range of 16 to 40 would have feedback phase jitter of only 2 to 3.2 ps rms.
In this low noise situation, a TDC with less than 3.2 ps of resolution would act essentially like a bang-bang PFD (BB-PFD). Existing wireline communication PLLs are predominantly integer-N designs with strict system-level requirements on the rms jitter. A DPLL designer targeting these applications, therefore, would have to face the challenging and ever-increasing requirements on TDC resolution, or to find a way of using a BB-PFD.
The effective gain of a BB-PFD is a function of the jitter on its input signals, with gain increasing as jitter decreases. For PLLs that use BB-PFDs, therefore, the overall transfer function of the PLL is strongly influenced by elements not within the PLL design itself (such as the noise levels on the reference clock input). This is highly undesirable for applications such as serial link I/O clocking that demand low synthesizer noise as measured over defined integration bandwidths. One way that this can be resolved is by abandoning the bang-bang PFD approach and pursuing a time-to-digital (TDC)-based architecture, but this approach has numerous drawbacks in terms of complexity, area, power, calibration requirements, and compatibility with integer-N frequency synthesis specifications typical to wireline applications.